EDGE1=EDGE1_0, IEN0=IEN0_0, IEN1=IEN1_0, DEN0=DEN0_0, STS1=STS1_0, STS0=STS0_0, DEN1=DEN1_0, EDGE0=EDGE0_0
Crossbar A Control Register 0
| DEN0 | DMA Enable for XBAR_OUT0 0 (DEN0_0): DMA disabled 1 (DEN0_1): DMA enabled |
| IEN0 | Interrupt Enable for XBAR_OUT0 0 (IEN0_0): Interrupt disabled 1 (IEN0_1): Interrupt enabled |
| EDGE0 | Active edge for edge detection on XBAR_OUT0 0 (EDGE0_0): STS0 never asserts 1 (EDGE0_1): STS0 asserts on rising edges of XBAR_OUT0 2 (EDGE0_2): STS0 asserts on falling edges of XBAR_OUT0 3 (EDGE0_3): STS0 asserts on rising and falling edges of XBAR_OUT0 |
| STS0 | Edge detection status for XBAR_OUT0 0 (STS0_0): Active edge not yet detected on XBAR_OUT0 1 (STS0_1): Active edge detected on XBAR_OUT0 |
| DEN1 | DMA Enable for XBAR_OUT1 0 (DEN1_0): DMA disabled 1 (DEN1_1): DMA enabled |
| IEN1 | Interrupt Enable for XBAR_OUT1 0 (IEN1_0): Interrupt disabled 1 (IEN1_1): Interrupt enabled |
| EDGE1 | Active edge for edge detection on XBAR_OUT1 0 (EDGE1_0): STS1 never asserts 1 (EDGE1_1): STS1 asserts on rising edges of XBAR_OUT1 2 (EDGE1_2): STS1 asserts on falling edges of XBAR_OUT1 3 (EDGE1_3): STS1 asserts on rising and falling edges of XBAR_OUT1 |
| STS1 | Edge detection status for XBAR_OUT1 0 (STS1_0): Active edge not yet detected on XBAR_OUT1 1 (STS1_1): Active edge detected on XBAR_OUT1 |